-----------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
-- 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- 
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-----------------------------------------------------------------------------

-----------------------------------------------------------------------------
--! @file 
--! @brief First communication test with the camera
--! @author BLANCHARD Remy <remyb718 at gmail dot com>
--!
--! Platform   : Spartan 3
--!
--! Description: This file just store the 12 first lines of the camera 
--!              (OV7620) and stop until a reset of the iMX
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;

-----------------------------------------------------------------------
entity cam2imx is
-----------------------------------------------------------------------
  port (
      clk_i          : in  std_logic;
      rst_i          : in  std_logic;
      
      -- camera side
      -- Y signal (see documentation)
      Y_i            : in  std_logic_vector(7 downto 0);
      -- UV signal (see documentation)
      UV_i           : in  std_logic_vector(7 downto 0);
      PCLK_i         : in  std_logic;
      HREF_i         : in  std_logic;
      VSYNC_i        : in  std_logic;
      FODD_i         : in  std_logic;

      -- iMX side
      DataxD_io      : inout std_logic_vector(15 downto 0);
      AddrxDI_i      : in std_logic_vector(12 downto 0);
      CSxBI_i        : in std_logic;
      WRxBI_i        : in std_logic;
      RDxBI_i        : in std_logic
  );
end cam2imx;

-----------------------------------------------------------------------
architecture cam2imx_1 of cam2imx is
-----------------------------------------------------------------------

-- declaration

    -- definition of the state machine elements
    type state_machine is (init,wait_Vsync_fall,record_val,
                           wait_imx_reset);
    signal current_state_s, next_state_s: state_machine;

    signal RAM_addr_s    : std_logic_vector(12 downto 0):="0000000000000";
    signal FoddRAMaddr_s : std_logic_vector(13 downto 0):="00000000000000";

    -- variable to know if camera pixels are valid
    signal fill_ram_s    : std_logic := '0';

    -- variable to know if we are in an active state
    signal sys_active_s  : std_logic := '0';

    -- write enable for the RAMs
    signal ram_enable_s: std_logic := '0';

    -- write the output
    signal DataOutRAMxD_s : std_logic_vector(15 downto 0):="0000000000000000";
    signal FoddOutRAMxD_s : std_logic_vector(15 downto 0):="0000000000000000";

    -- do we read Y/UV (0) or Food (1)
    signal DataToIMXType_s: std_logic := '0';

    -- to convert Fodd into a std_logic_vector
    signal RAM_Input_Fodd_s: std_logic_vector(0 downto 0);

begin
    -- the main program

    -- State machine for the RAM-fill
    --! First we wait for a falling edge on Vsync
    --! pour chaque front montant de PCLK
    --!   Si Href est à 1
    --!     on enregistre Y et U/V
    --!     on enregistre Fodd
    --!   fin si
    --!   (arret sur front montant de Vsync)
    --!   (arret sur overflow de la RAM)
    --! fin pour
    --! on attend l'écriture de l'iMX à l'@0x0001 pour un reset
   state_machine_p: process
   begin
     wait until rising_edge(clk_i);
     case current_state_s is
       when init   => 
         fill_ram_s<='0';
         sys_active_s<='0';
         if VSYNC_i='1' then
           next_state_s<=wait_Vsync_fall;
         end if;

       when wait_Vsync_fall => 
         fill_ram_s<='0';
         sys_active_s<='0';
         if VSYNC_i='0' then
           next_state_s<=record_val;
         end if;

       when record_val =>
         fill_ram_s<=HREF_i;
         sys_active_s<='1';
         if VSYNC_i='1' then
           -- back to the beginning to refresh the image
           -- don't care if overwriting while reading
           next_state_s<=wait_Vsync_fall;
         --elsif RAM_addr_s="1111111111111" then -- for design purpose
         elsif RAM_addr_s="0000000010000" then -- for simulation purpose
           -- the RAM is full
           next_state_s<=wait_imx_reset;
         end if;

       when wait_imx_reset =>
         fill_ram_s<='0';
         sys_active_s<='0';
         if WRxBI_i='0' and CSxBI_i='0' and AddrxDI_i="0000000000001" then
           next_state_s<=init;
         end if;

     end case;
   end process state_machine_p;

   -- virtual machine stepper
   next_state_process_p: process (rst_i,clk_i)
   begin
   if rst_i='1' then
     current_state_s<=init;
   elsif rising_edge(clk_i) then
     current_state_s<=next_state_s;
   end if;
   end process next_state_process_p;

   -- internal clock handle
   internal_clk_p : process(rst_i,clk_i)
   variable detect_ps : std_logic_vector(1 downto 0);
   begin
     if rst_i='1' then
       detect_ps(1) := '1';
       detect_ps(0) := '1';
       ram_enable_s<='0';
       RAM_addr_s<="0000000000000";
     elsif rising_edge (clk_i) then
         detect_ps(1) := detect_ps(0);
         detect_ps(0) := PCLK_i;
         if detect_ps = "01" and fill_ram_s='1' then
           RAM_addr_s<=std_logic_vector(unsigned(RAM_addr_s)+1);
           ram_enable_s<='1';
         elsif detect_ps = "10" then
           ram_enable_s<='0';
         elsif sys_active_s='0' then
           -- reset the RAM adresse
           -- this step may be useless because 0x1FFF+0x1=0x0000
           -- (on 13 bytes)
           RAM_addr_s<="0000000000000";
           ram_enable_s<='0';
         end if;
     end if;
   end process internal_clk_p;

  --! To read Y/UV, you must first write 0x0000 at @0x0002
  --! To read a 16 bit concatened values of FODD, you must first write
  --! 0x0001 at @0x0002
  -- Write data on bus for iMX
  OutputEnable: process(rst_i,clk_i)
  begin
    if rst_i='1' then
      DataxD_io <= (others  => 'Z');
      DataToIMXType_s<='0';
    elsif rising_edge(clk_i) then
      if (CSxBI_i='0' and RDxBI_i='0' and DataToIMXType_s='0') then
--        DataxD_io<= DataOutRAMxD_s;
        DataxD_io<="1111000011110000";
      elsif (CSxBI_i='0' and RDxBI_i='0' and DataToIMXType_s='1') then
--        DataxD_io<=FoddOutRAMxD_s;
        DataxD_io<="1010101010101010";
      elsif WRxBI_i='0' and CSxBI_i='0' and AddrxDI_i="0000000000010" 
        and DataxD_io="0000000000000000" then
        DataToIMXType_s<='0';
      elsif WRxBI_i='0' and CSxBI_i='0' and AddrxDI_i="0000000000010" 
        and DataxD_io="0000000000000001" then
        DataToIMXType_s<='1';
      else
        DataxD_io <= (others  => 'Z'); 
      end if;
    end if;
  end process OutputEnable;

  -- variables for technical reasons
  FoddRAMaddr_s<="0"&RAM_addr_s;
  RAM_Input_Fodd_p: process
  begin
    wait until rising_edge(clk_i);
    if FODD_i='0' then
      RAM_Input_Fodd_s<="0";
    else
      RAM_Input_Fodd_s<="1";
    end if;
  end process RAM_Input_Fodd_p;

  
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------

  -- Bits 0 et 1 de Y
  RAMB16_S2_S2_Y01 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => Y_i(1 downto 0),           -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(1 downto 0),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 2 et 3 de Y
  RAMB16_S2_S2_Y23 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => Y_i(3 downto 2),           -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(3 downto 2),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 4 et 5 de Y
  RAMB16_S2_S2_Y45 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => Y_i(5 downto 4),           -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(5 downto 4),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 6 et 7 de Y
  RAMB16_S2_S2_Y67 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => Y_i(7 downto 6),           -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(7 downto 6),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------

  -- Bits 0 et 1 de UV
  RAMB16_S2_S2_UV01 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => UV_i(1 downto 0),          -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(9 downto 8),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 2 et 3 de UV
  RAMB16_S2_S2_UV23 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => UV_i(3 downto 2),          -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(11 downto 10),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 4 et 5 de UV
  RAMB16_S2_S2_UV45 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => UV_i(5 downto 4),          -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(13 downto 12),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

  -- Bits 6 et 7 de UV
  RAMB16_S2_S2_UV67 : RAMB16_S2_S2
  generic map (
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"0", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"0", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL" 
  port map (
    DOA   => open,                      -- Port A 2-bit Data Output
    ADDRA => RAM_addr_s,                -- Port A 13-bit Address Input
    CLKA  => clk_i,                     -- Port A Clock
    DIA   => UV_i(7 downto 6),          -- Port A 2-bit Data Input
    ENA   => fill_ram_s,                -- Port A RAM Enable Input
    SSRA  => '0',                       -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,              -- Port A Write Enable Input

    DOB   => DataOutRAMxD_s(15 downto 14),-- Port B 2-bit Data Output
    ADDRB => AddrxDI_i,                 -- Port B 13-bit Address Input
    CLKB  => clk_i,                  -- Port B Clock
    DIB   => "00",                      -- Port B 2-bit Data Input
    ENB   => not CSxBI_i,               -- Port B RAM Enable Input
    SSRB  => '0',                       -- Port B Synchronous Set/Reset Input
    WEB   => '0'                        -- Port B Write Enable Input
  );

---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
  
  -- Fodd
  RAMB16_S1_S18_Fodd : RAMB16_S1_S18
  generic map (
  -- because of a bug in XST 
  -- INIT_A=>"0" => INIT_A=>X"0" and
  -- SRVAL_A=>"0" => SRVAL_A=>X"0" 
    INIT_A => X"0", --  Value of output RAM registers on Port A at startup
    INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
    SRVAL_A => X"0", --  Port A ouput value upon SSR assertion
    SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
    WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
    SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"     
  port map (
    DOA   => open,               -- Port A 1-bit Data Output
    ADDRA => FoddRAMaddr_s,      -- Port A 14-bit Address Input
    CLKA  => clk_i,              -- Port A Clock
    DIA   => RAM_Input_Fodd_s,   -- Port A 1-bit Data Input
    ENA   => fill_ram_s,         -- Port A RAM Enable Input
    SSRA  => '0',                -- Port A Synchronous Set/Reset Input
    WEA   => ram_enable_s,       -- Port A Write Enable Input

    DOB   => FoddOutRAMxD_s,     -- Port B 16-bit Data Output
    ADDRB => AddrxDI_i(9 downto 0),-- Port B 10-bit Address Input
    DOPB  => open,               -- Port B 2-bit Parity Output
    CLKB  => clk_i,           -- Port B Clock
    DIB   => "0000000000000000", -- Port B 16-bit Data Input
    DIPB  => "00",               -- Port B 2-bit parity Input
    WEB   => '0',                -- Port B Write Enable Input
    ENB   => not CSxBI_i,        -- Port B RAM Enable Input
    SSRB  => '0'                 -- Port B Synchronous Set/Reset Input
  );

end cam2imx_1; 

